This invention relates to digital signal processing (“DSP”) circuitry, and more particularly to arrays of DSP circuit modules or blocks that can optionally work together to perform DSP operations of greater complexity and/or greater mathematical or arithmetic precision, and that when thus needed to work together, can accommodate the possibility that a circuit defect may make a DSP block unusable.
Various circumstances may call for an integrated circuit to be fabricated with multiple instances of blocks or modules of DSP circuitry. An example of such an integrated circuit is a programmable logic device (“PLD”) or a field-programmable gate array (“FPGA”). Such a device may have a plurality of rows of various kinds of circuitry, such as relatively general-purpose programmable logic. Each such row may also include a block of DSP circuitry (i.e., circuitry that is hard-wired to at least some degree to perform a particular DSP function or a particular set of DSP functions). It can be desirable in such a situation to size the DSP blocks so that they fit within the (row) boundaries of the other circuitry in the row. This may mean that a DSP block is too small, by itself, to perform some DSP functions that it may be desired for the integrated circuit to perform. In such cases it would be desirable to facilitate optional “stitching together” of multiple DSP blocks in various ways so that larger DSP functions can be efficiently performed in two or more DSP blocks. However, a countervailing concern may be that if any portion of the circuitry associated with DSP blocks that need to be stitched together is not usable (e.g., because of a manufacturing defect in the integrated circuit), that can make it much more difficult or impossible to stitch together those DSP blocks. This may greatly increase the chances that a partly defective integrated circuit cannot be used at all.